This invention relates to MOS voltage precharge circuitry which is useful with many of today's dynamic MOS memory systems.
The use of an MOS transistor with the drain and the gate connected together to a precharge voltage pulse generator is well known for setting the potential of an address select line (of a dynamic p-channel MOS memory) connected to the source to one threshold voltage level above the low voltage level of the voltage pulse generator. One problem with this technique is that the potential of the address select line cannot be set closer than one threshold potential above the low voltage level of the voltage pulse generator. Accordingly, noise margin and transistor geometry are adversely affected.
One possible method for dynamically setting the potential of an address select line of a p-channel MOS memory system to a value which is equal to the lowest available level of a pulse generator is to use an MOS transistor with a "bootstrap" capacitor between the source and gate. The drain and source of the transistor are connected to a voltage pulse generator and an address select line, respectively. The potential of the gate is first dynamically set to one threshold level above the lowest power supply potential, and then thereafter the drain of the transistor is typically pulsed from a high power supply potential level to the lowest available power supply. As the source charges towards the drain potential, charge is coupled from the source via the capacitor to "bootstrap" the gate to a more negative level. The use of a sufficient size capacitor allows the lowering of the potential of the gate to at least one threshold level below that of the potential of the lowest available power supply. This permits the source to reach a potential that is equal to that of the lowest power supply. One problem with this method is that an additional input signal and additional timing requirements are placed on the entire system.
Another possible method of achieving the desired result is to use a first p-channel MOS transistor with the drain and gate connected together to a first voltage pulse generator and the source connected to an address select line. A first terminal of a capacitor is connected to the source and the second terminal is connected to a second voltage pulse generator. The gate and drain of the transistor are first pulsed to the potential level of the lowest available power supply. This sets the address select line potential to one threshold voltage above the lowest available power supply. A negative going voltage waveform is then applied to the second terminal of the capacitor to further lower the potential of the source. This allows the potential of the address select line to be lowered to a value which can be less than that of the lowest available power supply potential. One of the problems with this method is that it requires a separate capacitor for each circuit node to be set in potential. It also adds timing requirements and, in addition, the extra capacitance loads down the voltage pulse generators connected thereto.
It would be desirable to have precharge circuitry which can be utilized for simultaneously precharging many circuit nodes, which does not require a separate capacitor per node, and which requires essentially only one external input voltage pulse.